(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method that prevents damage to the alignment mark during steps of semiconductor device processing by creating an alignment mark comprising V-shaped grooves.
(2) Description of the Prior Art
The creation of semiconductor devices makes frequent use of creating overlying or other patterns of interacting device features that must be closely aligned with each other. Semiconductor device processing comprises the deposition and patterning of layers of semiconductor materials such as layers of dielectric or insulating materials, polysilicon layers in doped or undoped form or other layers of conductive material comprising for instance metal or metal alloys. The patterning of these layers, with the objective of creating specific device features therein, typically uses a photoresist mask overlying the layer that is to be patterned. The deposited layer of photoresist is exposed using a photomask that contains the pattern that is to be creating in the layer of photoresist, resulting in the photoresist mask. The photomask or reticle uses an alignment mark in the surface thereof for purposes of, in a cooperative effort with an alignment mark provided over the surface of a substrate, accurately aligning overlying or interacting patterns that must be created in mutually cooperative layers of semiconductor material. This task of accurate alignment of the patterns that are created in the various layers of a semiconductor device becomes more demanding as device features continue to decrease in size and as semiconductor devices continue to increase in density.
It must thereby further be considered that semiconductor devices are created using substrates of increased diameter, making uniform exposure of a deposited layer of semiconductor material over the surface of the substrate more difficult. A source of exposure that for instance is positioned centrally located to the surface of the substrate will radiate energy to the surface of the substrate such that this energy impacts the surface of the substrate under a decreasing angle as the impacted energy progresses towards the perimeter of the substrate. This therefore causes an asymmetry of exposure, whereby the center of the substrate is impacted under an angle of about ninety degrees, which angle however decreases towards the perimeter of the substrate. Where it therefore may be expected that, in the center of the substrate, features of a rectangular cross section can be created, this cross section will deviate significantly from the rectangular form the more the perimeter of the substrate is approached. This asymmetry results in a distortion of the signal that is reflected by the alignment mark, which is typically located in the perimeter of the substrate, a signal that is detected and processed by the exposure tool such as a photoresist exposure tool. The accuracy of alignment is also negatively affected by asymmetry in the alignment mark, which is typically provided over the surface of a substrate that is being processed. The invention addresses problems of asymmetry in the alignment mark.
U.S. Pat. No. 5,701,013 (Hsia et al.) shows a metrology pattern with overlay and Critical Dimension (CD) features.
U.S. Pat. No. 5,923,041 (Cresswell et al.) discloses an overlay target and measurement process.
U.S. Pat. No. 6,077,756 (Lin et al.), U.S. Pat. No. 5,677,091 (Barr et al.), U.S. Pat. No. 6,022,650 (Sogawa) and U.S. Pat. No. 5,776,645 (Barr et al.) are related patents.